The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2005

Filed:

Dec. 11, 2000
Applicant:

Kenji Yamauchi, Tokyo, JP;

Inventor:

Kenji Yamauchi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S005/00 ;
U.S. Cl.
CPC ...
Abstract

Positioning marksare formed at predetermined positions with respect to an active layerburied in an LD chip bodyIn an Au metallized layerfor solder joining on the active layermarksfor measurement are precisely formed by the same mask with which the positioning marksare formed. The marksfor measurement are arranged closer to the active layerin comparison with the positioning marksTherefore, the distances between the active layerand the marksfor measurement can be respectively measured with high accuracy. In mounting of the LD chip to a substrate in a passive alignment technique, relative positions of the active layer and the positioning marks are measured in advance with high accuracy and the LD chip can be mounted to the substrate by correcting both the relative positions. Thus, the LD chip is positioned with high accuracy to be mounted to the substrate. The LD chip and an optical waveguide, or an optical fiber arranged in the substrate, can be coupled to each other with high coupling efficiency.


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