Method and apparatus for implementing dram redundancy fuse latches using sram

Abstract

A method and structure is disclosed for serially storing and retrieving fuse information to and from a non-scannable static random access memory (SRAM) array within an embedded DRAM structure. The SRAM array is part of a scan chain and is connected to upstream and downstream latches that make up the scan chain. Various data is serially scanned into the scan chain. As the data flows through the entire scan chain, the invention counts the number of bits scanned into the embedded DRAM structure using a counter. The counter can be included within the embedded DRAM structure. After the counter counts to an amount equal to the number of bits of storage of all downstream scan latches in the scan chain, the invention loads the fuse information into a shift register. When the shift register is full, the invention loads the contents of the shift register to a SRAM line. The lengths of the shift register and the SRAM line are equal to a fuse word. The invention repeats these processes of loading the shift register and loading the SRAM array until the SRAM array is full. The fuse information is read from the SRAM array by simply specifying an address in the SRAM array.