The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6882211 B1

Expired

Date of Patent:

Apr. 19, 2005

Filed:

Feb. 05, 2003

Output circuit, input circuit, electronic circuit, multiplexer, demultiplexer, wired-or circuit, wired-and circuit, pulse-processing circuit, multiphase-clock processing circuit, and clock-multiplier circuit

Applicant:

Minoru Kozaki, Suwa, JP;

Inventor:

Minoru Kozaki, Suwa, JP;

Assignee:

Seiko Epson Corporation, , JP;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

My-Trang Nu Ton

Int. Cl.

CPC ...

H03K017/62 ;

U.S. Cl.

CPC ...

Abstract

A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG, TG, TG, and TG, these output nodes a to d are connected so as to have an equal wiring length, inverters IVand IVare disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IVand IVbecomes identical.

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Kozaki, Minoru. (2005). Output circuit, input circuit, electronic circuit, multiplexer, demultiplexer, wired-or circuit, wired-and circuit, pulse-processing circuit, multiphase-clock processing circuit, and clock-multiplier circuit (U.S. Patent No. 6882211). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6882211

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