High-performance programmable logic architecture

Abstract

A programmable logic device architecture. This programmable logic architecture includes a first logic block () containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (), which interfaces with the first logic block (), for performing JTAG functions, configuring the first logic block (), initializing the first logic block (), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block () may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (). The first logic block () includes a plurality of second logic blocks () which may be programmably coupled using a second programmable interconnect network (). The second programmable interconnect network () may be programmably coupled to the first programmable interconnect network (). Furthermore, the plurality of second logic blocks () include a plurality of third logic blocks () which may be programmably coupled using a third programmable interconnect network (). A signal from a third logic block () may be programmably coupled to the other logic blocks, the diagnostic block interface (), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.