The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Dec. 12, 2001
Hiroshi Tezuka, Tokyo, JP;
Hiroshi Tezuka, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A syndrome polynomial calculating circuit and a Reed-Solomon decoding circuit capable of performing a high-speed operation. Higher-order signals IIand Iare inputted to first to third Galois field multiplication circuits. For each of SSSand Sthe multipliers are a, a, a; a, a, a, a; a, a, a, a. Outputs of first to third multiplication circuits and Iare sent to an exclusive-OR gate, an output of which is sent to a D-F/F. An output of the D-F/F is sent to a fourth Galois field multiplication circuit and to an AND gate. For each of SSSand S, multipliers of the fourth multiplication circuit are a, a, a, a. An output of the fourth multiplication circuit is sent to a fifth input of the exclusive OR gate. Clocks are input to the D-F/F and to a counter. The counter value is reset by the inputting of a frame pulse. The counter value is L or H for the counter value of 0 to 4 or 5, respectively. A counter output is sent to the AND gate. A signal from the D-F/F is outputted only if the signal is H.