Pipelined processor and method using a profile register storing the return from exception address of an executed instruction supplied by an exception program counter chain for code profiling

Abstract

A pipeline processor having an exception program counter chain generates a return address in the exception program counter chain for an executing instruction. The return address is the point at which instruction execution should resume after an exception handler routine runs if the executing instruction incurs an exception. The return address is stored into a profiling register if and when the corresponding instruction completes execution. The profiling register is periodically sampled and a statistical profile is built of instructions executed in the processor by using the return addresses sampled. A sampled return address is identified as a branch delay instruction and included in the statistical profile if the sampled return address is that of a branch instruction which immediately precedes a branch delay instruction.