Synchronous semiconductor memory device having dynamic memory cells and operating method thereof

Abstract

A synchronous semiconductor memory device includes a memory cell array and a command decoder. In the memory cell array, dynamic memory cells are arranged in a matrix form. The command decoder decodes a plurality of commands in synchronism with an external clock signal. The plurality of commands are set by combinations of logical levels of a plurality of control pins at input timing of a first command and at input timing of a second command one cycle after the input timing of the first command. The command decoder includes a first decode section which determines a read operation, a second decode section which determines a write operation, and a third decode section which determines an auto-refresh operation. Setting of an auto-refresh command is determined only by a combination of the logical levels of the plurality of control pins at the input timing of the first command.