Semiconductor memory having a defective memory cell relieving circuit

Abstract

In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MCto MCis added with one column of redundant memory cells MCto MCand one word line of substitution information storing memory cells MCRAto MCRA. In only a first cycle after the power supply is turned on, the substitution information DRto DRj is read out from the substitution information storing memory cells by use of a writing/reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CSto CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CSto CSj so as to selectively connect the columns other than a defective column to an input/output line. Thus, a chip area overhead attributable to the installation of the defective memory cell relief circuit is minimized. In addition, an address comparing circuit for a defective memory cell substitution is no longer necessary, and an access time overhead attributable to the address substitution operation does not occur.