The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Aug. 15, 2002
John D. Leighton, Anoka, MN (US);
Scott M. O'brien, Eagan, MN (US);
Robert J. Wimmer, Hastings, MN (US);
Nameeta Krenz, Carver, MN (US);
Carl F. Elliott, Eden Prairie, MN (US);
Michael J. O'brien, St. Paul, MN (US);
Cameron C. Rabe, Inver Grove Heights, MN (US);
John D. Leighton, Anoka, MN (US);
Scott M. O'Brien, Eagan, MN (US);
Robert J. Wimmer, Hastings, MN (US);
Nameeta Krenz, Carver, MN (US);
Carl F. Elliott, Eden Prairie, MN (US);
Michael J. O'Brien, St. Paul, MN (US);
Cameron C. Rabe, Inver Grove Heights, MN (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
A write driver circuit selectively provides a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.