The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Apr. 04, 2003
Applicants:
Parvesh Swami, New Delhi, IN;
Namerita Khanna, New Delhi, IN;
Deepak Agarwal, Noida, IN;
Inventors:
Assignee:
STMicroelectronics Pvt. Ltd., Uttar Pradesh, IN;
Primary Examiner:
Int. Cl.
CPC ...
H03K019/00 ;
U.S. Cl.
CPC ...
Abstract
An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.