The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Jul. 18, 2003
Steven A. Rosenau, Mountain View, CA (US);
Mohammed E. Ali, Sunnyval, CA (US);
Brian E. Lemoff, Union City, CA (US);
Lisa A. Windover, San Francisco, CA (US);
Steven A. Rosenau, Mountain View, CA (US);
Mohammed E. Ali, Sunnyval, CA (US);
Brian E. Lemoff, Union City, CA (US);
Lisa A. Windover, San Francisco, CA (US);
Agilent Technologies, Inc., Palo Alto, CA (US);
Abstract
A folded flex circuit interconnect increases a number of interconnection pads of a grid array interface available to accommodate high count outputs from distinct circuit elements. The circuit interconnect includes a substrate capable of being folded, a conductor layer adjacent to a surface of the substrate, and a pad array having an interconnection pad connected to the conductor layer at a first end of the circuit interconnect. The pad array is part of the grid array interface. An optics module includes the folded flex circuit interconnect and an optical unit. The folded flex circuit interconnect further includes an electrical interface at a second end that is connected to the conductor layer. The folded flex circuit interconnect connects to the optical unit using the electrical interface. The circuit interconnect connects the optical unit to a motherboard using the pad array at the first end.