The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Jan. 09, 2003
Taner Dosluoglu, New York, NY (US);
Taner Dosluoglu, New York, NY (US);
Dialdg Semiconductor GmbH, Kirchheim, DE;
Abstract
A circuit and method are described which suppresses reset noise in active pixel sensor arrays. A circuit having a number of Nwells formed in a Psilicon epitaxial layer or a number of Pwells formed in an Nsilicon epitaxial layer is provided. A pixel is formed in each of the wells so that each of the wells is surrounded by silicon of the opposite polarity and an array of pixels is formed. Means are provided for selectively combining or binning adjacent Nor Pwells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated. The reset is accomplished using a PMOS transistor formed in each Nwell or an NMOS transistor formed in each Pwell. The selective binning is accomplished using NMOS or PMOS transistors formed in the region between adjacent wells. Conductive traces between adjacent wells can also be used to accomplish the selective binning.