The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2005

Filed:

Jan. 02, 2003
Applicants:

Devendra K. Sadana, Pleasantville, NY (US);

Stephen W. Bedell, Wappingers Falls, NY (US);

Tze-chiang Chen, Yorktown Heights, NY (US);

Kwang Su Choe, Mt. Kisco, NY (US);

Keith E. Fogel, Mohegan Lake, NY (US);

Inventors:

Devendra K. Sadana, Pleasantville, NY (US);

Stephen W. Bedell, Wappingers Falls, NY (US);

Tze-Chiang Chen, Yorktown Heights, NY (US);

Kwang Su Choe, Mt. Kisco, NY (US);

Keith E. Fogel, Mohegan Lake, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/36 ;
U.S. Cl.
CPC ...
Abstract

In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.


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