The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2005

Filed:

Aug. 08, 2003
Applicants:

Yutaka Ueda, Kawasaki, JP;

Hiroshi Yoshioka, Kawasaki, JP;

Inventors:

Yutaka Ueda, Kawasaki, JP;

Hiroshi Yoshioka, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C011/22 ;
U.S. Cl.
CPC ...
Abstract

In a memory cell array, a plurality of memory cells having ferroelectric capacitors are arranged. A plurality of sense amplifier circuits amplifies the potential of the bit line of each memory cell. A column decoder outputs activation signals to activate the sense amplifier circuits. Timing adjusting circuits have a ferroelectric capacitor for timing adjustment in transmitting the activation signals output from the column decoder to the sense amplifier circuits.


Find Patent Forward Citations

Ueda, Yutaka. (2005). Timing adjusting circuit and semiconductor memory device (U.S. Patent No. 6876568). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6876568

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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