Integrated modulator and demodulator configuration

Abstract

An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples. The multiplexer provides interpolated digital samples at four times the sample rate. The digital sign inverter negates selected digital samples according to Weaver modulation.