The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2005
Filed:
Oct. 19, 2001
Hiroshi Iwata, Ikoma-gun, JP;
Akihide Shibata, Nara, JP;
Seizo Kakimoto, Shiki-gun, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors () are formed on a P-type shallow well region (). The depth of a shallow device isolation region () on the P-type shallow well region () is less than the depth of the junction between an N-type deep well region () and the P-type shallow well region (). Therefore the field effect transistors () share the P-type shallow well region (). The P-type shallow well regions () independently of each other are easily formed since they are isolated from each other by a deep device isolation region () and the N-type deep well region ().