Memory cell, wafer, semiconductor component with memory cell having insulation collars and method for fabricating an insulating collar for a memory cell

Abstract

The invention relates to a DRAM memory cell having a trench filled with conductive material connected to a selection transistor by a connection having a vertical insulation collar arranged perpendicularly to a layer sequence of the memory cell. The vertical insulation collar is connected to a lateral insulation collar of the trench. This lateral insulation collar essentially extends perpendicular to the vertical insulation collar or is arranged laterally with respect to the vertical insulation collar. It is thus possible to provide a memory cell, a wafer and a semiconductor component that have a high integration density and a sufficient dielectric strength, and that efficiently suppress parasitic transistors. A method for fabricating a lateral insulating collar for a memory cell is also described.