The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2005
Filed:
Sep. 26, 2003
Kengo Takata, Tokyo, JP;
Tsutomu Yoshimura, Tokyo, JP;
Harufusa Kondo, Tokyo, JP;
Hironobu Ito, Tokyo, JP;
Kengo Takata, Tokyo, JP;
Tsutomu Yoshimura, Tokyo, JP;
Harufusa Kondo, Tokyo, JP;
Hironobu Ito, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V) in the capacitor (). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V) in a capacitor (). A differential amplifier circuit () generates appropriate voltages (Vand V) according to a design specification of the transistors (and) by amplifying the voltage values (Vand V) and outputs them. The voltages (Vand V) are impressed on respective back gates of the transistors (and), respectively.