The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2005

Filed:

Mar. 11, 2004
Applicants:

Chul Ho Ham, Gyeonggi-do, KR;

Byoung Dae Lee, Gyeonggi-do, KR;

Ho Keun Song, Gyeonggi-do, KR;

Young Geun Park, Gyeonggi-do, KR;

Inventors:

Chul Ho Ham, Gyeonggi-do, KR;

Byoung Dae Lee, Gyeonggi-do, KR;

Ho Keun Song, Gyeonggi-do, KR;

Young Geun Park, Gyeonggi-do, KR;

Assignee:

Mirae Corporation, Chunan-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R031/02 ;
U.S. Cl.
CPC ...
Abstract

Carrier module for a semiconductor device test handler including a carrier module body, a device seating part in an underside part of the carrier module body, at least one pair of first latches at opposite sides of the device seating part arranged opposite to, and movable away from, or close to, each other, for holding, or releasing opposite side parts of the semiconductor device seated on the device seating part, at least one pair of second latches rotatably fitted on opposite sides of the first latch, for holding an underside part of the semiconductor device seated on the device seating part, and releasing the semiconductor device interlocked with a releasing action of the first latch, a latch button fitted in an upper part of the carrier module to move in up/down directions and coupled to one end of the first latch, for moving up and down to make the first latch to move, and a first elastic member, and a second elastic member for elastic supporting of the first latch, and the second latch, thereby securely holding, transferring, and bringing the semiconductor device into contact with the test socket, for testing.


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