The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2005
Filed:
Jun. 10, 1999
Applicants:
Toshiyuki Nagata, Plano, TX (US);
Hiroyuki Yoshida, Plano, TX (US);
Masayuki Moroi, Richardson, TX (US);
Atsushi Satoh, Dallas, TX (US);
Inventors:
Toshiyuki Nagata, Plano, TX (US);
Hiroyuki Yoshida, Plano, TX (US);
Masayuki Moroi, Richardson, TX (US);
Atsushi Satoh, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L027/108 ; H01L029/76 ; H01L029/94 ; H01L031/119 ;
U.S. Cl.
CPC ...
Abstract
In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.