The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Apr. 18, 2003
Jong Seok Han, Taejon, KR;
Yong Seok Choi, Taejon, KR;
Sang Man Moh, Taejon, KR;
Myung-joon Kim, Taejon, KR;
Kee-wook Rim, Kyonggido Kwangju, KR;
Jong Seok Han, Taejon, KR;
Yong Seok Choi, Taejon, KR;
Sang Man Moh, Taejon, KR;
Myung-Joon Kim, Taejon, KR;
Kee-Wook Rim, Kyonggido Kwangju, KR;
Electronics and Telecommunication Research Institute, Taejon, KR;
Abstract
The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.