The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Jun. 11, 2003
Jonathan Byrn, Kasson, MN (US);
James Jensen, Eagan, MN (US);
Roy Perrigo, Henrietta, NY (US);
Donald Gabrielson, Rochester, MN (US);
Jonathan Byrn, Kasson, MN (US);
James Jensen, Eagan, MN (US);
Roy Perrigo, Henrietta, NY (US);
Donald Gabrielson, Rochester, MN (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration ('test backplane') for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the 'test backplane'. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.