The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Feb. 26, 2004
Kyung Whan Kim, Seoul, KR;
Kyung Whan Kim, Seoul, KR;
Hynix Semiconductor Inc., Kyungki-Do, KR;
Abstract
A power-up circuit comprises a first PMOS transistor connected between the power supply and a first node, wherein a gate terminal of the first PMOS transistor is connected to the ground, a first voltage divider for dividing the power upon a power up, a first NMOS transistor driven an output of the first voltage divider upon a power up and connected between the first node and the ground, an inverter having a plurality of PMOS transistors connected between the power supply and a second node, in which gate electrodes of the plurality of inverter are connected from each other and a second NMOS transistor connected between the second node and the ground and gate of the second NMOS transistor is connected to the plurality of the PMOS transistors, thereby inverting the potential of the first node, and a third NMOS transistor connected between the first node and the ground, wherein the third NMOS transistor is turned on by an output of the inverter, thereby preventing shifting faster than the potential of the first node.