The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2005

Filed:

Oct. 21, 2002
Applicants:

Steven Reder, Boring, OR (US);

Michael Berman, West Linn, OR (US);

Rennie Barber, Gresham, OR (US);

Inventors:

Steven Reder, Boring, OR (US);

Michael Berman, West Linn, OR (US);

Rennie Barber, Gresham, OR (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/31 ;
U.S. Cl.
CPC ...
Abstract

Application of an extremely low K material by the application of a laminate onto a wafer. The laminate preferably contains alternating layers of low K material and etch stop layers, and could be applied by rolling the laminate onto the wafer. An anneal process can be utilized to bond the film to the wafer. Conventional photo masking and etching techniques are then used to open vias and line areas in the film, and to deposit the next copper layer on the wafer. Electro polishing can be used to planarize or remove residual copper. Thereafter, an etch step can be performed to remove the excess material between the copper lines to leave an ultra low K region between the copper lines. The next layer of low K film can then be deposited, and the process repeated for all subsequent metal layering.


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