The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2005

Filed:

May. 30, 2003
Applicants:

Sang-jin Lee, Seoul, KR;

Tae-soo Park, Seongnam, KR;

Young-gun Ko, Seongnam, KR;

Inventors:

Sang-jin Lee, Seoul, KR;

Tae-soo Park, Seongnam, KR;

Young-gun Ko, Seongnam, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/8234 ; H01L021/336 ;
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor device having an L-shaped spacer comprises forming a gate pattern on a transistor region of a semiconductor substrate. A disposable spacer is formed on an insulating layer of sidewalls of the gate pattern. Deeply doped source/drain regions are formed aligned with the disposable spacer of the transistor region and in the semiconductor substrate of a resistor region. The disposable spacer and the first insulating layer are removed. A shallowly doped source/drain region is formed aligned with the sides of the gate pattern and adjacent to the deeply doped source/drain region of the transistor region. An L-shaped spacer is formed adjacent to the sidewalls of the gate pattern of the transistor region. A suicide formation protecting layer pattern is simultaneously formed on the resistor region. A metal silicide is formed on an upper surface of the gate electrode, the deeply doped source/drain regions.


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