The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2005

Filed:

Oct. 09, 2002
Applicants:

Paul C. F. Tong, San Jose, CA (US);

Ming-dou Ker, Hsinchu, TW;

Ping Ping Xu, San Jose, CA (US);

Inventors:

Paul C. F. Tong, San Jose, CA (US);

Ming-Dou Ker, Hsinchu, TW;

Ping Ping Xu, San Jose, CA (US);

Assignee:

Pericom Semiconductor Corp., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H009/00 ;
U.S. Cl.
CPC ...
Abstract

Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.


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