The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2005
Filed:
Sep. 19, 2002
Robert J. Drost, Mountain View, CA (US);
Robert J. Bosnyak, San Jose, CA (US);
Robert J. Drost, Mountain View, CA (US);
Robert J. Bosnyak, San Jose, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block. In a particular embodiment, the method includes selecting a logic state of a digital input; applying the digital input to a parasitic capacitance block having an output, the output having a first capacitance when the digital input is in first logic state and a second capacitance when the digital input is in a second logic state; and adjusting a capacitance with respect to a second circuit node within the integrated circuit by applying the output to the second circuit node.