The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2005
Filed:
Jun. 10, 2003
Severino A. Legaspi, Jr., Santa Clara, CA (US);
Manickam Thavarajah, San Jose, CA (US);
Maurice O. Othieno, Union City, CA (US);
Pradip D. Patel, Redwood City, CA (US);
Severino A. Legaspi, Jr., Santa Clara, CA (US);
Manickam Thavarajah, San Jose, CA (US);
Maurice O. Othieno, Union City, CA (US);
Pradip D. Patel, Redwood City, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.