The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2005

Filed:

Dec. 13, 2001
Applicants:

Hiroyuki Uchiyama, Tachikawa, JP;

Atsushi Ogishima, Tachikawa, JP;

Shoji Shukuri, Koganei, JP;

Inventors:

Hiroyuki Uchiyama, Tachikawa, JP;

Atsushi Ogishima, Tachikawa, JP;

Shoji Shukuri, Koganei, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8242 ; H01L021/20 ;
U.S. Cl.
CPC ...
Abstract

A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.


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Uchiyama, Hiroyuki. (2005). Semiconductor integrated circuit device and the process of manufacturing the same for reducing the size of a memory cell by making the width of a bit line than a predetermined minimum size (U.S. Patent No. 6867092). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6867092

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