The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2005
Filed:
Apr. 04, 2001
Robert J. Devins, Essex Junction, VT (US);
Paul J. Ferro, South Burlington, VT (US);
Peter D. Lafauci, Holly Springs, NC (US);
Kenneth A. Mahler, Essex Junction, VT (US);
David W. Milton, Underhill, VT (US);
Robert J. Devins, Essex Junction, VT (US);
Paul J. Ferro, South Burlington, VT (US);
Peter D. LaFauci, Holly Springs, NC (US);
Kenneth A. Mahler, Essex Junction, VT (US);
David W. Milton, Underhill, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.