The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2005
Filed:
Jan. 10, 2003
Jack Siu Cheung Lo, San Jose, CA (US);
Shankar Lakkapragada, San Jose, CA (US);
Shi-dong Zhou, Milpitas, CA (US);
Jack Siu Cheung Lo, San Jose, CA (US);
Shankar Lakkapragada, San Jose, CA (US);
Shi-dong Zhou, Milpitas, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.