The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2005

Filed:

Jun. 09, 2003
Applicants:

Carl Anthony Monzel, Iii, Lakeville, MN (US);

Michael Dillon, Richfield, MN (US);

Bret Alan Oeltjen, Elko, MN (US);

Inventors:

Carl Anthony Monzel, III, Lakeville, MN (US);

Michael Dillon, Richfield, MN (US);

Bret Alan Oeltjen, Elko, MN (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/177 ;
U.S. Cl.
CPC ...
Abstract

A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.


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