The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2005

Filed:

Dec. 24, 2003
Applicants:

Ross E. Teggatz, McKinney, TX (US);

Reed W. Adams, Plano, TX (US);

Suribhotla V. Rajasekhar, Plano, TX (US);

Inventors:

Ross E. Teggatz, McKinney, TX (US);

Reed W. Adams, Plano, TX (US);

Suribhotla V. Rajasekhar, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R031/27 ;
U.S. Cl.
CPC ...
Abstract

The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present invention provides an overstress test structure () that comprises a first transistor (), having a first terminal coupled to ground, a second terminal coupled to a control signal (), and a third terminal coupled to a first end of a first resistive element (). A first voltage source () is coupled to the second end of the first resistive element. A second resistive element () is intercoupled between the second end of the first resistive element and ground. A second transistor () has a first terminal coupled to the second end of the first resistive element, a second terminal coupled to the first end of the first resistive element, and a third terminal coupled to a first node (). A third resistive element () is intercoupled between the third terminal of the second transistor and ground; and a third transistor () has a first terminal coupled () to the oxide structure, a second terminal coupled to the first end of the first resistive elerment, and a third terminal coupled to a second voltage source ().


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