The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2005

Filed:

Dec. 26, 2002
Applicants:

Satoru Kaneko, Kumagaya, JP;

Toshiyuki Ohkoda, Oizumi-machi, JP;

Takao Myono, Menuma-machi, JP;

Inventors:

Satoru Kaneko, Kumagaya, JP;

Toshiyuki Ohkoda, Oizumi-machi, JP;

Takao Myono, Menuma-machi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L029/76 ; H01L029/94 ; H01L031/062 ; H01L031/113 ;
U.S. Cl.
CPC ...
Abstract

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N−S and/or a second drain layer N−D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.


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