The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2005
Filed:
May. 21, 2003
Christopher A. Ludden, Pittsford, NY (US);
Richard Alexander Erhart, Tempe, AZ (US);
Mark D. Kuhns, Peoria, AZ (US);
Arif Alam, Chandler, AZ (US);
Christopher A. Ludden, Pittsford, NY (US);
Richard Alexander Erhart, Tempe, AZ (US);
Mark D. Kuhns, Peoria, AZ (US);
Arif Alam, Chandler, AZ (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample data from a data line. The sampled data is checked against a preamble pattern (a sequence of known data). A digital deskew control block selects one of the clock phases after analyzing the results of preamble pattern check such that subsequently received data is sampled with the appropriately selected clock phase.