Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor

Abstract

The vertical transistor includes, on a semiconductor substrate, a vertical pillarhaving one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layersituated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first regionresting on the gate dielectric layerand a second regionfacing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavitiesS,D.