The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2005

Filed:

Sep. 27, 2002
Applicants:

John T. Phan, Williston, VT (US);

Michael Armand Roberge, Milton, VT (US);

Inventors:

John T. Phan, Williston, VT (US);

Michael Armand Roberge, Milton, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C008/00 ;
U.S. Cl.
CPC ...
Abstract

Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least one of approaching and acquiring lock; and then thereafter determining a Lock Latency value in response to examining a DLL output clock signal generated in response to the first clock signal.


Find Patent Forward Citations

Phan, John. (2005). Method and apparatus for dll lock latency detection (U.S. Patent No. 6859413). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6859413

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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