The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2005
Filed:
Feb. 22, 2002
Mitsuaki Nagasaka, Kawasaki, JP;
Daisuke Miura, Kawasaki, JP;
Masayuki Okamoto, Kawaskai, JP;
Hiroyuki Honda, Kawasaki, JP;
Toshio Arakawa, Kawasaki, JP;
Shuji Yoshida, Kawasaki, JP;
Kenji Yoshida, Kawasaki, JP;
Kenji Kobayashi, Nagoya, JP;
Mitsuaki Nagasaka, Kawasaki, JP;
Daisuke Miura, Kawasaki, JP;
Masayuki Okamoto, Kawaskai, JP;
Hiroyuki Honda, Kawasaki, JP;
Toshio Arakawa, Kawasaki, JP;
Shuji Yoshida, Kawasaki, JP;
Kenji Yoshida, Kawasaki, JP;
Kenji Kobayashi, Nagoya, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.