The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2005
Filed:
Nov. 30, 2001
Adrian Messmer, Zurich, CH;
Stefan Koch, Zurich, CH;
Adrian Messmer, Zurich, CH;
Stefan Koch, Zurich, CH;
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Abstract
System (), e.g. a System on a chip (SoC), comprising a system bus (), a high-speed functional block () operably linked to the system bus (), and a high-speed clock line () for applying a high-speed clock to the high-speed functional block (). The system () further comprises a peripheral bus (), a low-speed functional block () operably linked to this peripheral bus (), a circuitry () for generating a wait signal (PWAIT), a low-speed clock line () for applying a low-speed clock (PCLK) to the low-speed functional block (), a select line () for feeding a select signal (PSEL) from the peripheral bus () to the low-speed functional block (), an enable line () for applying a clock enable signal (PCLKEN) to the circuitry (), and a wait line () for feeding the wait signal (PWAIT) to the high-speed functional block (). The circuitry () generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).