The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2005

Filed:

Oct. 26, 2001
Applicants:

Makoto Usui, Osaka, JP;

Hironori Deguchi, Kadoma, JP;

Takahiro Ochi, Kyoto, JP;

Yasuhiro Ueki, Sagamihara, JP;

Mitsuhiko Ohta, Yokohama, JP;

Yutaka Osada, Fujisawa, JP;

Inventors:

Makoto Usui, Osaka, JP;

Hironori Deguchi, Kadoma, JP;

Takahiro Ochi, Kyoto, JP;

Yasuhiro Ueki, Sagamihara, JP;

Mitsuhiko Ohta, Yokohama, JP;

Yutaka Osada, Fujisawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B007/0045 ;
U.S. Cl.
CPC ...
Abstract

Crosstalk between tracks, land prepit leakage, and effects of recording power modulation can cause the wobble signal period to change irregularly, thereby producing jitter in the recording clock which is derived by frequency multiplying the wobble signal. This problem is resolved by a recording clock generating circuit having an arrangement to average the wobble signal period, a timer for generating a rectangular wave with substantially the same period as the average period, and a frequency multiplying PLL for multiplying the timer output. The period averaging arrangement in particular determines the approximate average period at every wobble period and reflects the phase difference between the wobble signal and the timer in the timer setting so as to improve recording clock stability.


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