The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2005
Filed:
May. 30, 2003
Johnny Chan, Fremont, CA (US);
Jinshu Son, Saratoga, CA (US);
Ken Kun YE, Fremont, CA (US);
Tinwai Wong, Fremont, CA (US);
Johnny Chan, Fremont, CA (US);
Jinshu Son, Saratoga, CA (US);
Ken Kun Ye, Fremont, CA (US);
Tinwai Wong, Fremont, CA (US);
Atmel Corporation, San Jose, CA (US);
Abstract
A signal integrity checking circuit for an integrated circuit detects whether signal condition involving loading of data into storage elements is valid or improper and flags the result. The integrity circuit includes a plurality of adjacently positioned and substantially similar storage elements, which are clocked by a common clock line and loaded from a common data input line. A common reset line may also be provided. The storage elements may be flip-flops, latches, RAM, etc. A logic gate, such as a NAND gate, receives the storage element outputs and flags improper loading of data. Inverters on the input and output sides of one storage element force it to the opposite state from the other storage element. The signal integrity checking circuit is valuable for ensuring proper loading during power-on or start-up, and at other times when loading of data may occur.