The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2005
Filed:
Sep. 16, 1999
Richard L. Weisfield, Los Altos, CA (US);
Richard L. Weisfield, Los Altos, CA (US);
Xerox Corporation, Stamford, CT (US);
Abstract
A clamping circuit including a clamping diode, a bias line, and a clamp line is incorporated into a pixel circuit of amorphous silicon sensor arrays. The clamp diode in each pixel prevents the voltage across the photodiode from dropping below a specific threshold. By keeping the photodiode under reverse bias even under conditions that may otherwise saturate the pixel, image lag is reduced. In full fill factor amorphous silicon sensor arrays, a clamping circuit includes a clamp TFT, a bias plane, a clamp line, and a drain line. The clamp TFT reduces lag and blooming by draining off excess current developed under overexposure conditions. A method to globally reset a sensor array and a method to test and repair a TFT matrix in full fill factor sensor arrays without damaging the overlying collection electrode and sensor layer are also provided.