The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2005

Filed:

Jul. 09, 2002
Applicants:

David Dearn, Malmesbury, GB;

John Stuart Malcolm, Headley Hants, GB;

Axel Pannwitz, Lenningen, DE;

Inventors:

David Dearn, Malmesbury, GB;

John Stuart Malcolm, Headley Hants, GB;

Axel Pannwitz, Lenningen, DE;

Assignee:

Dialog Semiconductor GmbH, Kirchheim/Teck-Nabern, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F001/40 ;
U.S. Cl.
CPC ...
Abstract

A method and a circuit to achieve a low drop-out voltage regulator with a wide output load range has been achieved. A fast loop is introduced in the circuit. The circuit is internally compensated and uses a capacitor to ensure that the internal pole is more dominant than the output pole as in standard Miller compensation. The quiescent current is set being proportional to the output load current. No explicit low power drive stage is required. The whole output range is covered by one output drive stage. By that means the total consumption of quiescent or wasted current is reduced. An excellent PSRR is achieved due to load dependent bias current.


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