The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2005
Filed:
Mar. 03, 2003
Youzou Fukagawa, Tochigi, JP;
Youzou Fukagawa, Tochigi, JP;
Canon Kabushiki Kaisha, Tokyo, JP;
Abstract
A method for determining a chip arrangement on a wafer. The method includes steps of generating a grid array in which rectangles are arranged in a grid pattern, the rectangle corresponding to a chip in size, an apex of the rectangle being a grid point, extracting a plurality of the grid points, having respective distances, from an origin, not greater than a constant defined by an available area on the wafer, from the grid array, forming a region, of which a form corresponds to the available area and which has the original and one of the extracted grid points on its circumference, on the grid array, with respect to each of the plurality of the grid points extracted in the extracting step, and determining a chip arrangement on the wafer based on a region, which includes a maximum number of the rectangles, formed in the forming step.