The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2005
Filed:
Oct. 02, 2002
Masuo Inui, Kasugai, JP;
Takashi Kurihara, Kasugai, JP;
Masuo Inui, Kasugai, JP;
Takashi Kurihara, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A method for designing power supply wiring of a semiconductor integrated circuit having a logic circuit. A first power consumption value of the logic circuit is calculated based on logic connection information, and the power supply wiring is laid out in accordance with the first power consumption value. Logic modification connection information relating to the modified logic circuit is generated when the logic circuit is modified after the power supply wiring is laid out. A second power consumption value of the modified logic circuit is calculated based on the logic modification connection information. When the second power consumption value exceeds the first power consumption value, it is determined that the power supply wiring must be re-laid out. It is thus easily determined whether to re-lay out the power supply wiring without performing power supply network analysis.