The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2005
Filed:
Mar. 10, 2003
Applicants:
Masayoshi Tojima, Kasuya-gun, JP;
Hiromasa Nakajima, Machida, JP;
Masahiro Oohashi, Kasuya-gun, JP;
Yasuo Kohashi, Kasuya-gun, JP;
Inventors:
Masayoshi Tojima, Kasuya-gun, JP;
Hiromasa Nakajima, Machida, JP;
Masahiro Oohashi, Kasuya-gun, JP;
Yasuo Kohashi, Kasuya-gun, JP;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C007/00 ; G11C008/00 ;
U.S. Cl.
CPC ...
Abstract
The time required for access to a SDRAM () is extracted from the layout of an integrated circuit (), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit () is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit () in the designing stage is realized.