The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2005

Filed:

Aug. 01, 2003
Applicants:

Youngwoo Kim, Seoul, KR;

Jae Sung Lee, Daejeon, KR;

Kyoung Park, Daejeon, KR;

Sang Man Moh, Daejeon, KR;

Yong Youn Kim, Daejeon, KR;

Myung-joon Kim, Daejeon, KR;

Kee-wook Rim, Daejeon, KR;

Inventors:

Youngwoo Kim, Seoul, KR;

Jae Sung Lee, Daejeon, KR;

Kyoung Park, Daejeon, KR;

Sang Man Moh, Daejeon, KR;

Yong Youn Kim, Daejeon, KR;

Myung-Joon Kim, Daejeon, KR;

Kee-Wook Rim, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C016/04 ;
U.S. Cl.
CPC ...
Abstract

In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.


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