Phase locked loop circuit having main and auxiliary frequency dividers and multiple phase comparisons

Abstract

A PLL circuit including a generating means () for generating a plurality of reference signals (fRto fR) having mutually differing phases, a main frequency divider () dividing an output signal (fVCO) of a voltage-controlled oscillator () by a frequency-division ratio of N1, an auxiliary frequency divider () dividing an output (fV') of the main frequency divider by a frequency-division ratio of N2, a distribution circuit () distributing an output (Q, Q, Q) of the auxiliary frequency divider as a plurality of feedback signals (fVto fV), and phase comparators (to) comparing the reference signals with the feedback signals to output error signals (ERto ER). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.