The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2005

Filed:

Aug. 14, 2001
Applicants:

Brian Christopher Hart, Georgetown, KY (US);

Shauna Marie Leis, Georgetown, KY (US);

Gary Raymond Williams, Lexington, KY (US);

Inventors:

Brian Christopher Hart, Georgetown, KY (US);

Shauna Marie Leis, Georgetown, KY (US);

Gary Raymond Williams, Lexington, KY (US);

Assignee:

Lexmark International, Inc., Lexington, KY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B21D053/76 ; B23P017/00 ; G01D015/00 ; G11B005/127 ;
U.S. Cl.
CPC ...
Abstract

The invention provides an improved method for grit blasting slots in a silicon wafer. The method includes, providing a silicon wafer having a first surface and a second surface, the first surface containing resistive, conductive and insulative layers defining individual semiconductor components, applying a first substantially permanent non-water soluble layer selected from silane, photoresist materials and a combination of a silane layer and a photoresist layer to the first surface of the wafer to provide a first substantially permanent layer thereon, applying a water-soluble protective material to the first layer to provide a second layer, grit blasting slots in the wafer corresponding to the individual semiconductor components, and subsequently, removing the water-soluble protective layer from the wafer. The protective layer provides enhanced protection for the electrical components on a silicon wafer during a grit blasting process so that a higher yield of useable semiconductor chips may be made.


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