The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2005

Filed:

Aug. 18, 2000
Applicants:

Eiji Moro, Hitachinaka, JP;

Ken Sodeyama, Hitachinaka, JP;

Hiroyuki Hori, Hitachi, JP;

Katsuyuki Watanabe, Mito, JP;

Akifumi Tabata, Naka, JP;

Inventors:

Eiji Moro, Hitachinaka, JP;

Ken Sodeyama, Hitachinaka, JP;

Hiroyuki Hori, Hitachi, JP;

Katsuyuki Watanabe, Mito, JP;

Akifumi Tabata, Naka, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 595 ;
U.S. Cl.
CPC ...
Abstract

The present invention relates to a video signal processing apparatus for outputting an inputted video signal after subjecting the video signal to time axis correction, particularly to a video signal processing apparatus preferable in the case of subjecting the video signal to image compression. In the case in which a nonstandard signal is inputted to an image compression circuit of an MPEG2 encoder or the like, a drawback of freezing image or generating block noise or the like is resolved. A time axis correcting circuit stores an input signal to a memory and reads the input signal at a timing delayed from V synchronization of the input signal by a predetermined time period. For that purpose, a read synchronizing signal generator is reset at respective input field. A reset position is set to a position preceding the read V synchronization position by 3H through 10H. It is detected whether the input signal is a non-interlace signal or a field length thereof is deviated from a standard value and in these cases, odd/even order or synchronization timing of a synchronizing signal is corrected. Further, when the input signal is a nonstandard signal, the input signal is outputted without passing through the image compression circuit by a changeover switch.


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